Honeywell HG-1700 PC/104 SDLC Interface : UAV Control & Flight Data Recording.

HG-1700-104 PC/104 SDLC Interface

for the Honeywell HG1700/1900 Inertial Measurement Unit

Information about the HG-1700 IMU must be obtained directly from Honeywell. We do not supply any information on the HG1700.

Interface shown in custom interface mounting frame.

Note: This interface does not include the HG1700 as shown. The mounting frames are optional. Contact Honeywell for the HG-1700.

HG-1700-104

MS-DOS and Windows are trademarks of Microsoft Corporation.

ROM-DOS is a trademark of Datalight Corporation.

Red Hat Linux is a trademark of Red Hat Corporation.

Lindows is a trademark of Lindows.com, Inc.

QNX is a trademark of QNX Software Systems Ltd.

HG-1700 is a product of Honeywell.

Description: The IMU-1700-104 PC/104 (ISA) module is a high performance FPGA based SDLC interface for acquiring inertial data from a Honeywell HG-1700/1900 or compatible IMU. The interface is register based and can be accessed to control operation and acquire IMU data and time information. All IO registers have the capability of being either directly accessed via the FPGA base IO address block or as individually mapped IO addresses in the ISA IO space. It is recommended that all registers be IO mapped.

The interface uses two programmable logic devices. A 5V Xilinx CPLD which is JTAG programmed at the factory and an Altera FPGA. The Xilinx is used to provide a stable configuration port for runtime device configuration of the FPGA as well as providing buffered 5V drive capability for the ISA bus to and from the FPGA. Configuration of the FPGA is via Passive Serial Configuration from the Xilinx and is done via the supplied configuration software which at boot time uploads the raw binary format file to the Altera FPGA. The supplied DOS configuration software uploads the Altera ACEX configuration code and initializes the IO registers defined in an initialization file.

SDLC Interface: The SDLC interface is clocked as required by the HG1700 IMU. The HG1700 outputs 2 message types and the interface can acquire each message type individually or simultaneously. Message filtering is per register value. Upon completion of a message receive the interface will place the message size in bytes in the message size register and will generate a interrupt to the host processor to read the message.

SDLC Time Tag: A 10 Mhz clock provides 100 nS time tag resolution for each incoming inertial message relative to a GPS 1PPS signal. Upon the rising edge of the GPS 1PPS a 3 byte counter is reset to 0. Upon the first incoming bit of a SDLC message the value is stored in this register as an unsigned integer count since the GPS 1PPS. In addition to the time tag information the interface provides constant correction of the TTL clock by inserting (or deleting) error counts each PPS cycle based upon the number of counts between consecutive PPS edges. The corrected and uncorrected clock counts are readable from the ACEX memory map and are IO mappable. The count since the 1PPS is also corrected each PPS cycle based upon linear interpolation to correct for drift each cycle. The count is available as both corrected and uncorrected time tag per the ACEX memory map.

1PPS Input: The interface provides a SMA input for a TTL level 1PPS signal from a GPS to reset the IMU Time tag once per second. In addition the 1PPS input is buffered and provided as a interrupt output to the host processor. Once the PPS generates an interrupt the host processor writes a 0x80 to register 0x40 which clears the pending interrupt. This register is also IO mappable.

RS-422 Interface: The interface also provides a 16C550 UART RS-422 high speed interface for general purpose serial IO. This interface is IO mapped per the hg1700.ini configuration file and is typically mapped to a IO space such as 0x2e8. This interface supports RS-422 only at speeds up to 920 kbs. Operation is as a normal serial port. Interface is unavailable until the FPGA is configured.

OS Support: Currently only DOS is supported per customer requirement. Source is available for the configuration routine and can be ported for other operating systems. This interface requires direct IO and IRQ handlers. Custom driver can be developed for additional charge.